DIF=AHB_IF0, CSIZE=CHK_1, WRIP=DONE, DWIDTH=BYTE, SWREQ=HWR_CONNECTED, DAM=FIXED_AM, TYPE=MEM_TRAN, DSYNC=PER2MEM, MEMSET=NORMAL_MODE, MBSIZE=SINGLE, INITD=IN_PROGRESS, RDIP=DONE, SAM=FIXED_AM, PERID=HSMCI, SIF=AHB_IF0
Channel Configuration Register
| TYPE | Channel x Transfer Type 0 (MEM_TRAN): Self-triggered mode (memory-to-memory transfer). 1 (PER_TRAN): Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). |
| MBSIZE | Channel x Memory Burst Size 0 (SINGLE): The memory burst size is set to one. 1 (FOUR): The memory burst size is set to four. 2 (EIGHT): The memory burst size is set to eight. 3 (SIXTEEN): The memory burst size is set to sixteen. |
| DSYNC | Channel x Synchronization 0 (PER2MEM): Peripheral-to-memory transfer. 1 (MEM2PER): Memory-to-peripheral transfer. |
| SWREQ | Channel x Software Request Trigger 0 (HWR_CONNECTED): Hardware request line is connected to the peripheral request line. 1 (SWR_CONNECTED): Software request is connected to the peripheral request line. |
| MEMSET | Channel x Fill Block of memory 0 (NORMAL_MODE): Memset is not activated. 1 (HW_MODE): Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. |
| CSIZE | Channel x Chunk Size 0 (CHK_1): 1 data transferred 1 (CHK_2): 2 data transferred 2 (CHK_4): 4 data transferred 3 (CHK_8): 8 data transferred 4 (CHK_16): 16 data transferred |
| DWIDTH | Channel x Data Width 0 (BYTE): The data size is set to 8 bits 1 (HALFWORD): The data size is set to 16 bits 2 (WORD): The data size is set to 32 bits |
| SIF | Channel x Source Interface Identifier 0 (AHB_IF0): The data is read through the system bus interface 0. 1 (AHB_IF1): The data is read through the system bus interface 1. |
| DIF | Channel x Destination Interface Identifier 0 (AHB_IF0): The data is written through the system bus interface 0. 1 (AHB_IF1): The data is written though the system bus interface 1. |
| SAM | Channel x Source Addressing Mode 0 (FIXED_AM): The address remains unchanged. 1 (INCREMENTED_AM): The addressing mode is incremented (the increment size is set to the data size). 2 (UBS_AM): The microblock stride is added at the microblock boundary. 3 (UBS_DS_AM): The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. |
| DAM | Channel x Destination Addressing Mode 0 (FIXED_AM): The address remains unchanged. 1 (INCREMENTED_AM): The addressing mode is incremented (the increment size is set to the data size). 2 (UBS_AM): The microblock stride is added at the microblock boundary. 3 (UBS_DS_AM): The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. |
| INITD | Channel Initialization Terminated (this bit is read-only) 0 (IN_PROGRESS): Channel initialization is in progress. 1 (TERMINATED): Channel initialization is completed. |
| RDIP | Read in Progress (this bit is read-only) 0 (DONE): No active read transaction on the bus. 1 (IN_PROGRESS): A read transaction is in progress. |
| WRIP | Write in Progress (this bit is read-only) 0 (DONE): No active write transaction on the bus. 1 (IN_PROGRESS): A write transaction is in progress. |
| PERID | Channel x Peripheral Hardware Request Line Identifier 0 (HSMCI): HSMCI 1 (SPI0_TX): SPI0_TX 2 (SPI0_RX): SPI0_RX 5 (QSPI_TX): QSPI_TX 6 (QSPI_RX): QSPI_RX 7 (USART0_TX): USART0_TX 8 (USART0_RX): USART0_RX 9 (USART1_TX): USART1_TX 10 (USART1_RX): USART1_RX 11 (USART2_TX): USART2_TX 12 (USART2_RX): USART2_RX 13 (PWM0): PWM0 14 (TWIHS0_TX): TWIHS0_TX 15 (TWIHS0_RX): TWIHS0_RX 16 (TWIHS1_TX): TWIHS1_TX 17 (TWIHS1_RX): TWIHS1_RX 18 (TWIHS2_TX): TWIHS2_TX 19 (TWIHS2_RX): TWIHS2_RX 20 (UART0_TX): UART0_TX 21 (UART0_RX): UART0_RX 22 (UART1_TX): UART1_TX 23 (UART1_RX): UART1_RX 24 (UART2_TX): UART2_TX 25 (UART2_RX): UART2_RX 26 (UART3_TX): UART3_TX 27 (UART3_RX): UART3_RX 28 (UART4_TX): UART4_TX 29 (UART4_RX): UART4_RX 30 (DACC0): DACC0 31 (DACC1): DACC1 32 (SSC_TX): SSC_TX 33 (SSC_RX): SSC_RX 34 (PIOA): PIOA 35 (AFEC0): AFEC0 36 (AFEC1): AFEC1 37 (AES_TX): AES_TX 38 (AES_RX): AES_RX 39 (PWM1): PWM1 40 (TC0): TC0 41 (TC3): TC3 42 (TC6): TC6 43 (TC9): TC9 44 (I2SC0_TX_LEFT): I2SC0_TX_LEFT 45 (I2SC0_RX_LEFT): I2SC0_RX_LEFT 48 (I2SC0_TX_RIGHT): I2SC0_TX_RIGHT 49 (I2SC0_RX_RIGHT): I2SC0_RX_RIGHT |